Datasheet4U Logo Datasheet4U.com

IS61DDSB21M18C Datasheet 18Mb DDR-II SIO SYNCHRONOUS SRAM

Manufacturer: ISSI (now Infineon)

Overview: IS61DDSB21M18C IS61DDSB251236C 1Mx18, 512Kx36 18Mb DDR-II (Burst 2) SIO SYNCHRONOUS SRAM APRIL.

General Description

The 18Mb IS61DDSB251236C and IS61DDSB21M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a separate I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Seperate I/O read and write ports.
  • Synchronous pipeline read with self-timed late write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only.
  • Two input clocks (C and.