IS61DDSB251236C Description
The 18Mb IS61DDSB251236C and IS61DDSB21M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a separate I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
IS61DDSB251236C Key Features
- 512Kx36 and 1Mx18 configuration available
- On-chip delay-locked loop (DLL) for wide data valid
- Seperate I/O read and write ports
- Synchronous pipeline read with self-timed late write
- Double Data Rate (DDR) interface for read and
- Fixed 2-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control
- Two input clocks (C and C#) for data output control
- Two echo clocks (CQ and CQ#) that are delivered