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MPC990 - (MPC990 / MPC991) LOW VOLTAGE PLL CLOCK DRIVER

Key Features

  • an external differential ECL/PECL feedback to the PLL. This external feedback feature allows for the MPC991’s use as a “zero” delay buffer. The propagation delay between the input reference and the output is dependent on the input reference frequency. The selection of higher reference frequencies will provide near zero delay through the device. The PLL_En, Ref_Sel and the Test_Clk input pins provide a means of bypassing the PLL and driving the output buffers directly. This allows the user to sin.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MPC992 LOW VOLTAGE PLL CLOCK DRIVER
MPC993 Dynamic Switch PLL Clock Driver
MPC9990 Low Voltage PLL Clock Driver
MPC9992 3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR
MPC99J93 Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage PLL Clock Driver The MPC990/991 is a 3.3V compatible, PLL based ECL/PECL clock driver. The fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC990/991 makes the device ideal for Workstation, Mainframe Computer and Telecommunication applications. The MPC990 and MPC991 devices are identical except in the interface to the reference clock for the PLL. The MPC990 offers an on–board crystal oscillator as the PLL reference while the MPC991 offers a differential ECL/PECL input for applications which need to lock to an existing clock signal. Both designs offer a secondary single–ended ECL clock for system test capabilities.