MPC99J93 Overview
The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance.
MPC99J93 Key Features
- Fully Integrated PLL
- Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32--Lead LQFP Packaging