MPC9992 - 3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR

Motorola Semiconductor (now NXP Semiconductors)

General Description

The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock.

The reference clock frequency and the divider for the feedback path determine the VCO frequency.

Both must be selected to match the VCO frequency range.

Key Features

MPC9992 3.3V.

📥 Download Datasheet

MPC9992 3.3 diffrerential ecl/pecl pll clock generator by Motorola Semiconductor (now NXP Semiconductors) - Datasheet Preview

Datasheet Details

Part number	MPC9992
Manufacturer	Motorola Semiconductor (now NXP Semiconductors)
File Size	143.83 KB
Description	3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR
Datasheet	MPC9992 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Number: MPC9992/D Rev 2, 04/2002 Product Preview 3.3V Differential ECL/PECL PLL Clock Generator The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using SiGe technology and a fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC9992 makes the device ideal for workstation, mainframe computer and telecommunication applications. With output frequencies up to 400 MHz and output skews less than 150 ps1 the device meets the needs of the most demanding clock applications. The MPC9992 offers a differential PECL input and a crystal oscillator interface. All control signals are LVCMOS compatible. Features MPC9992 3.