256K-bit Datasheet | Specifications & PDF Download

M27C4002 4 Mbit (256Kb x16) UV EPROM and OTP EPROM 5V ± 10% SUPPLY VOLTAGE in READ OPERATION FAST ACCESS TIME: 45ns LOW POWER CONSUMPTION: – Active Cu

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CY7C1041G CY7C1041GE 4-Mbit (256K words × 16 bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words × 16 bit) Static RAM with Error-Corr

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M27W400 4 Mbit (512Kb x8 or 256Kb x16) Low Voltage UV EPROM and OTP EPROM s 2.7 to 3.6V LOW VOLTAGE in READ OPERATION READ ACCESS TIME: – 80ns at VCC

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HY29F400 4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory KEY FEATURES n 5 Volt Read, Program, and Erase – Minimizes system-level power requirement

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HY29F400 4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory KEY FEATURES n 5 Volt Read, Program, and Erase – Minimizes system-level power requirement

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K7N403601A K7N401801A www.DataSheet4U.com 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAM TM Revision Hist

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MITSUBISHI LSls MsM4464P-12, -15 262 144-BIT(65 536-WORD BY 4-BIT) DYNAMIC RAM DESCRIPTION This is family of 65536-word by 4-bit dynamic RAMs, fabric

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HM62256B Series 256k SRAM (32-kword × 8-bit) ADE-203-135F (Z) Rev. 6.0 Nov. 13, 1997 Description The Hitachi HM62256B Series is a CMOS static RAM org

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HY29F002T 2 Megabit (256K x 8), 5 Volt-only, Flash Memory KEY FEATURES n 5 Volt Read, Program, and Erase – Minimizes system-level power requirements n

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Freescale Semiconductor Data Sheet Document Number: MR2A16A Rev. 4, 6/2007 256K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM Introduction The MR

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CY7C1378C 9-Mbit (256K x 32) Pipelined SRAM with NoBL™ Architecture Features • Pin-compatible and functionally equivalent to ZBT® devices • Internall

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K6F2008T2E Family Document Title Preliminary CMOS SRAM www.DataSheet4U.com 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision

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K6F4016U4G Family Preliminary CMwwOwS.DaStaSRheAet4MU.com Document Title 256Kx16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision

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BL24C256A 256K bits (32768×8) Features ⚫ Compatible with all I2C bidirectional data transfer protocol ⚫ Memory array: – 256 Kbits (32 Kbytes) of EEPRO

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E PRELIMINARY 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY n High Performance Read  80/120 ns Max Access Time 40 ns Max. Output Enable Time n

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FUJITSU SEMICONDUCTOR DATA SHEET Memory FRAM DS501-00023-0v01-E 2 M (256 K × 8) Bit SPI MB85RS2MT ■ DESCRIPTION MB85RS2MT is a FRAM (Ferroelectric

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MITSUBISHI LSls M5M4256P-12, -15, -20 262 144-BIT (262 144-WORD BY I-BIT) DYNAMIC RAM DESCRIPTION This is a fami Iy of 262 144-word by 1-bit dynamic

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