74HC10 Datasheet | Specifications & PDF Download

TECHNICAL DATA Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS IN74HC10A The IN74HC10A is identical in pinout to the LS/ALS10. The devi

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74HC10; 74HCT10 Triple 3-input NAND gate Rev. 4 — 8 January 2021 Product data sheet 1. General description The 74HC10; 74HCT10 is a triple 3-input N

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CD74HC10, CD54HC10 SCHS128D – AUGUST 1997 – REVISED JULY 2021 CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltag

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CD74HC10, CD54HC10 SCHS128D – AUGUST 1997 – REVISED JULY 2021 CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltag

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HD74HC10 Triple 3-input NAND Gates Features • • • • • High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Lo

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HD74HC107 Dual J-K Flip-Flops (with Clear) Description This flip-flop is edge sensitive to the clock input and change state on the negative going tra

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HD74HC108 Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock) Description This flip-flop is edge sensitive to the clock input and change

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HD74HC109 Dual J-K Flip-Flops (with Preset and Clear) Description Each flip-flop has independent J, K , preset, clear and clock inputs and Q and Q ou

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HD74HC109 Dual J-K Flip-Flops (with Preset and Clear) REJ03D0561-0200 (Previous ADE-205-434) Rev.2.00 Oct 11, 2005 Description Each flip-flop has i

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HD74HC10 Triple 3-input NAND Gates Features • High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF) • High Output Current: Fanout of 10 LSTTL Loads

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06

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TECHNICAL DATA KK74HC109A Dual J-K Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The KK74HC109A is identical in pinout to the LS/A

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TECHNICAL DATA KK74HC10A Triple 3-Input NAND Gate High-Performance Silicon-Gate CMOS The KK74HC10A is identical in pinout to the LS/ALS10. The devic

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74HC10-Q100; 74HCT10-Q100 Triple 3-input NAND gate Rev. 2 — 8 January 2021 Product data sheet 1. General description The 74HC10-Q100; 74HCT10-Q100

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74HC109-Q100; 74HCT109-Q100 Dual JK flip-flop with set and reset; positive-edge-trigger Rev. 2 — 1 April 2020 Product data sheet 1. General descri

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Data sheet acquired from Harris Semiconductor SCHS140E March 1998 - Revised October 2003 CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Dual J-K Flip-F

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Data sheet acquired from Harris Semiconductor SCHS139D March 1998 - Revised October 2003 CD54HC107, CD74HC107, CD74HCT107 Dual J-K Flip-Flop with Res

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CD74HC10, CD54HC10 SCHS128D – AUGUST 1997 – REVISED JULY 2021 CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltag

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SN54HC109, SN74HC109 SCLS470C – MARCH 2003 – REVISED JUNE 2022 SNx4HC109 Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 1 Features

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74HC109; 74HCT109 Dual JK flip-flop with set and reset; positive-edge-trigger Rev. 5 — 5 August 2021 Product data sheet 1. General description The

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