Motorola
SN74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs
Rating:
1
★
(4 votes)
Texas Instruments
SN74LS112A - Dual J-K Negative-Edge-Triggered Flip-Flops
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device JM38510/07102BEA
Status Package Type Package Pins Package
Rating:
1
★
(4 votes)
Hitachi Semiconductor
HD74LS112 - Dual J-K Negative-edge-triggered Flip-Flops
19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
Hit
Rating:
1
★
(3 votes)
Fairchild Semiconductor
DM74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000
DM74
Rating:
1
★
(3 votes)
Motorola
74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs
Rating:
1
★
(3 votes)
Fairchild Semiconductor
74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000
DM74
Rating:
1
★
(3 votes)
National Semiconductor
DM74LS112A - NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS
www.datasheet4u.com
www.datasheet4u.com
www.datasheet4u.com
Rating:
1
★
(3 votes)
Renesas
HD74LS112P - Dual J-K Negative-edge-triggered Flip-Flops
HD74LS112
Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear)
REJ03D0426–0300 Rev.3.00
Jul.13.2005
Features
• Ordering Information
P
Rating:
1
★
(3 votes)
Renesas
HD74LS112 - Dual J-K Negative-edge-triggered Flip-Flops
HD74LS112
Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear)
REJ03D0426–0300 Rev.3.00
Jul.13.2005
Features
• Ordering Information
P
Rating:
1
★
(2 votes)
Hitachi Semiconductor
74LS112 - Dual J-K Negative-edge-triggered Flip-Flops
19.20 20.00 Max 16 9 7.40 Max 6.30
Unit: mm
1 1.3
1.11 Max
8
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
Hit
Rating:
1
★
(1 votes)