LS11 Datasheet | Specifications & PDF Download

19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hit

(60 views)

TRIPLE 3-INPUT AND GATE SN54/74LS11 VCC 14 13 12 11 10 9 8 TRIPLE 3-INPUT AND GATE LOW POWER SCHOTTKY 1234567 GND GUARANTEED OPERATING RANGES

(42 views)

54LS11 DM54LS11 DM74LS11 Triple 3-Input AND Gates June 1989 54LS11 DM54LS11 DM74LS11 Triple 3-Input AND Gates General Description This device contai

(38 views)

DM74LS11 Triple 3-Input AND Gate August 1986 Revised March 2000 DM74LS11 Triple 3-Input AND Gate General Description This device contains three inde

(34 views)

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs

(33 views)

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are desi

(33 views)

SN54LS11, SN54S11, SN74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE-AND GATES SDLS131 – APRIL 1985 – REVISED MARCH 1988 PRODUCTION DATA information is curre

(30 views)

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74

(29 views)

www.DataSheet4U.com www.DataSheet4U.com 1.0 1.1 S1 0.7 0.7 2.7 1.3 4.3 S2 1.2 0.7 0.6 0.7 0.7 0.7 1.0 1.1 S1 0.7 2.7 1.3 0.7 3.1 1.

(28 views)

www.datasheet4u.com www.datasheet4u.com www.datasheet4u.com

(28 views)

SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set in

(28 views)

All in 1, Li Battery Charger Controller IC LS11, LS2811 Features MOS , . , , (Pre-charge), . ; . . , , , , . . IC , (Fast Charge) . SOP-8

(28 views)

HD74LS11 / HD74LS15 Triple 3-input Positive AND Gates / Triple 3-input Positive AND Gates (with Open Collector Outputs) REJ03D0397–0300 Rev.3.00 Jul.1

(28 views)

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device JM38510/07102BEA Status Package Type Package Pins Package

(27 views)

Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0

(26 views)

SN54LS11, SN54S11, SN74LS11, SN74S11 TRIPLE 3-INPUT POSITIVE-AND GATES SDLS131 – APRIL 1985 – REVISED MARCH 1988 PRODUCTION DATA information is curre

(26 views)

HD74LS112 Dual J-K Negative-edge-triggered Flip-Flops (with Preset and Clear) REJ03D0426–0300 Rev.3.00 Jul.13.2005 Features • Ordering Information P

(26 views)

DM74LS11 Triple 3-Input AND Gate August 1986 Revised March 2000 DM74LS11 Triple 3-Input AND Gate General Description This device contains three inde

(25 views)

SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set in

(24 views)

OPTIREG™ linear voltage regulator TLS115B0LD High-precision voltage tracker Features • 150 mA current capability • Very high tracking accuracy • Outp

(24 views)