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K561TM2 - 2-stage (Master-slave) D flip-flop
Корпус: DIP-14 Микросхема К561ТМ2 представляет собой два двухступенчатых (master-slave) D-триггера со входами асинхронной установки и сброса и против.7476 - Dual Master-Slave J-K Flip-Flops
DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs September 1986 Revised July 2001 DM7476 Dual Master-Slave J-K .TC4027 - DUAL J-K MASTER-SLAVE FLIP FLOP
TC4027BP/BF/BFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4027BP,TC4027BF,TC4027BFN TC4027B Dual J-K Master-Slave Flip Flop TC4027.DM7476 - Dual Master-Slave J-K Flip-Flop
DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs September 1986 Revised February 2000 DM7476 Dual Master-Slave .CD4027BE - CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP
Data sheet acquired from Harris Semiconductor SCHS032C − Revised October 2003 The CD4027B types are supplied in 16-lead hermetic dual-in-line ceramic .DM7473 - Dual Master-Slave J-K Flip-Flop
DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs September 1986 Revised February 2000 DM7473 Dual Master-Slave J-K Flip-.CD4027BCN - Dual J-K Master/Slave Flip-Flop
CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset October 1987 Revised January 1999 CD4027BC Dual J-K Master/Slave Flip-Flop with Set and .74S112 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S1.CD4027BF - CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP
Data sheet acquired from Harris Semiconductor SCHS032C − Revised October 2003 The CD4027B types are supplied in 16-lead hermetic dual-in-line ceramic .DM7476 - Dual Master-Slave J-K Flip-Flops
5476 DM5476 DM7476 Dual Master-Slave J-K Flip-Flops with Clear Preset and Complementary Outputs June 1989 5476 DM5476 DM7476 Dual Master-Slave J-K F.HCF4095B - GATE J-K MASTER-SLAVE FLIP-FLOPS
HCC/HCF4095B HCC/HCF4096B GATE J-K MASTER-SLAVE FLIP-FLOPS . . . . . . . 16 MHz TOGGLE RATE (typ.) AT VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT.CD4027BMS - CMOS Dual J-K Master-Slave Flip-Flop
CD4027BMS December 1992 CMOS Dual J-K Master-Slave Flip-Flop Pinout CD4027BMS TOP VIEW Features • High Voltage Type (20V Rating) • Set - Reset Capab.TC4027BP - DUAL J-K MASTER-SLAVE FLIP-FLOP
TC4027BP/BF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC4027BP, TC4027BF TC4027B Dual J-K Master-Slave Flip Flop TC4027B is J-K mast.MC10131 - Dual Type D Master-Slave Flip-Flop
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual Type D Master-Slave Flip-Flop The MC10131 is a dual master–slave type D flip–flop. Asynchronous Set (S) and.CD4095BMS - CMOS Gated J-K Master-Slave Flip-Flops
CD4095BMS CD4096BMS December 1992 CMOS Gated J-K Master-Slave Flip-Flops Pinouts NC 1 RESET 2 J1 3 J2 4 J3 5 Q 6 VSS 7 Features • Set-Reset Capabili.