74LS73A
Fairchild Semiconductor
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Dual negative-edge-triggered master-slave j-k flip-flops.
DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
August 1986 Revised March 2000
DM74LS73A Dua.
📁 Related Datasheet
74LS73 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops
(Fairchild Semiconductor)
DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
August 1986 Revised March 2000
DM74LS73A Dua.
74LS73 - Dual J-K Flip-Flops
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.
74LS73 - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
(Motorola)
SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These dual flip-flops are.
74LS73A - Dual J-K Flip-Flops
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.
74LS74 - LOW-POWER SCHOTTKY
(ON Semiconductor)
SN74LS74A Dual D-Type Positive Edge-Triggered Flip-Flop
The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high sp.
74LS74 - Dual Positive-Edge-Triggered D Flip-Flops
(Fairchild Semiconductor)
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
August 1986 Revised March 2000
DM74LS74A Dual Posit.
74LS74 - Dual D-type Positive Edge-triggered Flip-Flops
(Hitachi Semiconductor)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max
1.30
7 7.62
0.51 Min
2.54 Min 5.06 Max
2.54 ± 0.25
0.48 ± 0.10
0.25 – 0.05 0° – 15°
+ 0.
74LS74 - Dual Positive-Edge-Triggered D Flip-Flops
(National Semiconductor)
54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs
June 1989
54LS74 DM54LS74A DM74LS74.
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