PhaseLink Corporation Datasheet | Specifications & PDF Download

PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference c

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PLL102-03 Low Skew Output Buffer FEATURES Frequency range 75 ~ 180MHz. Internal phase locked loop will allow spread spectrum modulation on reference c

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(Preliminary) PL611s-17 1.8V-3.3V PicoPLL TM KHz to MHz Programmable Clock FEATURES • Advanced Programmable PLL design for lowfrequency (kHz) input

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PLL102-10 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference c

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Preliminary www.DataSheet4U.com PLL520-88/-89 Low Phase Noise VCXO (9.5-65MHz) PIN CONFIGURATION FEATURES • • • • • • • 19MHz to 65MHz fundamental

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P521-23 Low Phase Noise PECL VCXO (100MHz to 200MHz) PAD ASSIGNMENT AND DESCRIPTION Pin # 1 2 3 www.DataSheet4U.com4 Name OSCOFFSEL GNDOSC VCON XIN X

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PLL520-00 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) DIE CONFIGURATION 65 mil FEATURES • • 100MHz to 200MH

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(Preliminary) PL610-01 1.8V to 3.3V, 1MHz to 130MHz XO IC FEATURES  Wide frequency coverage, programmable, advanced oscillator design.  Programmab

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(Preliminary) PL611s-15 1.8V-3.3V PicoPLL TM 32K Programmable Clock FEATURES • Advanced Programmable PLL design for lowfrequency (KHz) input applica

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Preliminary P521-38 Low Phase Noise PECL VCXO (65MHz to 130MHz) FEATURES • 65MHz to 130MHz Fundamental Mode Crystal. • Output range: 65MHz – 130MHz.

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PLL102-05 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spectrum modulation on reference cl

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Preliminary PLL102-109 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up

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Preliminary PLL103-03 DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS FEATURES Generates 24-output buffers from one input. Supports up to 4 DDR DIM

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PLL520-05/-06/-07/-08/-09 www.DataSheet4U.com Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PIN CONFIGURATION (Top View) VDD XIN X

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PLL520-28/-29 www.DataSheet4U.com Low Phase Noise VCXO (for 120-200MHz Fund Xtal) PIN CONFIGURATION (Top View) FEATURES • • • • • • • • 120MHz to 20

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PLL520-38/-39 www.DataSheet4U.com PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) PIN CONFIGURATION VDD XIN XOUT N/C N/C OE 1 2 3 4 5 6

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PLL520-38/-39 www.DataSheet4U.com PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) PIN CONFIGURATION VDD XIN XOUT N/C N/C OE 1 2 3 4 5 6

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Preliminary www.DataSheet4U.com PLL520-88/-89 Low Phase Noise VCXO (9.5-65MHz) PIN CONFIGURATION FEATURES • • • • • • • 19MHz to 65MHz fundamental

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(Preliminary) PL611s-06 Low-Power Programmable Quick Turn Clock T M FEATURES • Advanced low-power, space saving programmable PLL design • Very low

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(Preliminary) PL611s-15 1.8V-3.3V PicoPLL TM 32K Programmable Clock FEATURES • Advanced Programmable PLL design for lowfrequency (KHz) input applica

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