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AK8181F Datasheet 3.3V LVPECL 1:4 Clock Fanout Buffer

Manufacturer: AKM (Asahi Kasei Microdevices)

General Description

The AK8181F is a member of AKM’s LVDS clock fanout buffer family designed for telecom, networking and computer applications, requiring a range of clocks with high performance and low skew.

The AK8181F distributes 4 buffered clocks.

AK8181F are derived from AKM’s long-termexperienced clock device technology, and enable clock output to perform low skew.

Overview

AK8181F Preliminary 3.3V LVDS 1:4 Clock Fanout Buffer AK8181F.

Key Features

  • Four differential 3.3V LVDS outputs Selectable differential PCLK0p/n or LVPECL clock inputs PCLK0p/n pair can accept the following differential input levels; LVDS, LVPECL, LVHSTL, SSTL, HCSL PCLK1p/n supports the following input types; LVPECL, CML, SSTL Clock output frequency up to 650MHz Translates any single-ended input signal to 3.3V LVDS levels with resistor bias on PCLK0n input Output skew : 30ps (maximum) Part-to-part skew : 600ps (maximum) Propagation delay : 2.5ns (maximum) Operating Tem.