* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
* Can support up to 133-MHz bus operations with zero wait states — Dat.

1] The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371C/ CY7C1373C is equipped.

CY7C1371B

CY7C1371D

CY7C1371DV25

CY7C1371KV33

CY7C1371KVE33

CY7C1371S

CY7C1370B

CY7C1370C

CY7C1370CV25

CY7C1370D

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