CY7C1371C architecture
18-mbit (512k x 36/1m x 18) flow-through sram with nobl architecture.18-mbit (512k x 36/1m x 18) flow-through sram with nobl architecture.
* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
* Can support up to 133-MHz bus operations with zero wait states — Dat.
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The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371C/ CY7C1373C is equipped.
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