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CY7C1371D - 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM

Download the CY7C1371D datasheet PDF (CY7C1373D included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 18-mbit (512 k x 36/1 m x 18) flow-through sram.

Description

The CY7C1371D/CY7C1373D is a 3.3 V, 512 K × 36/1 M × 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion.

Features

  • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles.
  • Supports up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin-compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow through operation.
  • Byte write capability.
  • 3.3 V/2.5 V I/O power supply (VDDQ).
  • Fast clock-to-output ti.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1373D_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

  • CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)
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Other Datasheets by Cypress Semiconductor
  • CY7C1371DV25 - (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM
  • CY7C1371B - (CY7C1371B / CY7C1373B) 512K x 36/1M x 18 Flow-Thru SRAM
  • CY7C1371KV33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
  • CY7C1371KVE33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
  • CY7C1370B - (CY7C1370B / CY7C1372B) 512K X 36/1M X 18 Pipelined SRAM
  • CY7C1370DV25 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
  • CY7C1370KV25 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM
  • CY7C1370KV33 - 18-Mbit (512K x 36/1M x 18) Pipelined SRAM

Full PDF Text Transcription

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CY7C1371D CY7C1373D 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features ■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 6.
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