* Pin-compatible with and functionally equivalent to ZBT™
* Supports 250-MHz bus operations with zero wait states
* Available speed grades are 250, 200, and 166 MHz
* Internally self-timed output buffer control to eliminate the need to use asynchronous OE
* Fully registered (inpu
CY7C1354CV25 Datasheet (1.32 MB)
CY7C1354CV25
Cypress Semiconductor
1.32 MB
9-mbit (256k x 36/512k x 18) pipelined sram.
CY7C1354CV25 CY7C1356CV25 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ .
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