CY7C1373DV25
Features
- No Bus Latency™ (No BL™) architecture eliminates dead cycles between write and read cycles
- Can support up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin patible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow-through operation
- Byte Write capability
- 2.5V core power supply (VDD)
- 2.5V I/O power supply (VDDQ)
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
- Synchronous self-timed writes
- Asynchronous Output Enable
- Available in JEDEC-standard lead-free 100-Pin TQFP, lead-free and non-lead-free 119-Ball BGA and 165- Ball FBGA package.
- Three chip enables for simple depth expansion
- Automatic Power-down feature available using ZZ mode or CE deselect
- IEEE 1149.1 JTAG-patible Boundary Scan
- Burst Capability- linear or interleaved burst order
- Low...
