* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
* Supports up to 133-MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin-compatible and functionally equivalent to ZBT™ devices
* Internally self-timed outp
CY7C1373D Datasheet (802.19 KB)
CY7C1373D
Cypress Semiconductor
802.19 KB
18-mbit (512 k x 36/1 m x 18) flow-through sram.
CY7C1371D CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL.
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