CY7C1373D - 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM

Cypress Semiconductor

Datasheet Details

Part number	CY7C1373D
Manufacturer	Cypress Semiconductor
File Size	802.19 KB
Description	18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
Datasheet	CY7C1373D_CypressSemiconductor.pdf

No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles.
Supports up to 133-MHz bus operations with zero wait states.
Data is transferred on every clock.
Pin-compatible and functionally equivalent to ZBT™ devices.
Internally self-timed output buffer control to eliminate the need to use OE.
Registered inputs for flow through operation.
Byte write capability.
3.3 V/2.5 V I/O power supply (VDDQ).
Fast clock-to-output ti.

📁 CY7C1373D Similar Datasheet

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Other Datasheets by Cypress Semiconductor

CY7C1373DV25 - (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM
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CY7C1373KV33 - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
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Published: Mar 12, 2010 |