CY7C1373D Datasheet - Cypress Semiconductor

CY7C1373D 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM

CY7C1373D Features

* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles

* Supports up to 133-MHz bus operations with zero wait states

* Data is transferred on every clock

* Pin-compatible and functionally equivalent to ZBT™ devices

* Internally self-timed outp

Datasheet Details

CY7C1373D

Cypress Semiconductor

802.19 KB

18-mbit (512 k x 36/1 m x 18) flow-through sram.

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