CY7C1373C

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

Cypress

* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

* Can support up to 133-MHz bus operations with zero wait states

* Data is transferred on every clock

* Pin compatible and functionally equivalent to ZBT™ devices

* Int

CY7C1373C

Cypress

791.68 KB

18-mbit (512k x 36/1m x 18) flow-through sram with nobl architecture.

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