CY7C1373C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

Cypress

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Datasheet Details

Part number	CY7C1373C
Manufacturer	Cypress
File Size	791.68 KB
Description	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
Datasheet	CY7C1373C_Cypress.pdf

CY7C1373C Product details

Description

1] The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.The CY7C1371C/ CY7C1373C is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.This feature dramatically improves the throughput of data through the SRAM, especially in systems

Features

No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
Can support up to 133-MHz bus operations with zero wait states.
Data is transferred on every clock.
Pin compatible and functionally equivalent to ZBT™ devices.
Internally self-timed output buffer control to eliminate the need to use OE.
Registered inputs for flow-through operation.
Byte Write capability.
3.3V/2.5V I/O power supply.

📁 CY7C1373C Similar Datasheet

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Published: Aug 19, 2005 |