CY7C1373DV25 Datasheet (Cypress Semiconductor) - (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM

CY7C1373DV25, (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM

1] The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x 36/1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

The CY7C1371DV25/CY7C1373DV25 is equipped with the advanced No Bus Latency (NoBL)

CY7C1373DV25 Features

* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles

* Can support up to 133-MHz bus operations with zero wait states

* Data is transferred on every clock

* Pin compatible and functionally equivalent to ZBT™ devices

* Int