CY7C1471BV33 Overview
CY7C1471BV33 CY7C1473BV33 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™.
CY7C1471BV33 Key Features
- No bus latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
- Supports up to 133 MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin patible and functionally equivalent to ZBT™ devices
- Internally self timed output buffer control to eliminate the need
- Registered inputs for flow through operation
- Byte write capability
- 3.3 V/2.5 V I/O supply (VDDQ)
- Fast clock-to-output times
- 6.5 ns (for 133 MHz device)