CY7C1522JV18 - 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture

Cypress (Infineon)

General Description

The CY7C1522JV18, CY7C1529JV18, CY7C1523JV18, and CY7C1524JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O (DDR-II SIO) architecture.

The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array.

Key Features

Functional.

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CY7C1522JV18 72-mbit ddr-ii sio sram 2-word burst architecture by Cypress (Infineon) - Datasheet Preview

Datasheet Details

Part number	CY7C1522JV18
Manufacturer	Cypress (Infineon)
File Size	690.50 KB
Description	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Datasheet	CY7C1522JV18 Datasheet

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Part Number	Description
CY7C1522AV18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1522KV18	72-Mbit DDR II SIO SRAM 2-Word Burst Architecture
CY7C1522V18	72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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CY7C1520V18	1.8V Synchronous Pipelined SRAM

Full PDF Text Transcription (Reference)

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CY7C1522JV18, CY7C1529JV18 CY7C1523JV18, CY7C1524JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description The CY7C1522JV18, CY7C1529JV18, CY7C1523JV18, and CY7C1524JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate I/O (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus.