72-mbit Ddr-ii Sio Sram 2-word Burst Architecture
| Part number | CY7C1522JV18 |
|---|---|
| Manufacturer | Cypress (now Infineon) |
| File Size | 690.50 KB |
| Description | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| Datasheet | CY7C1522JV18_CypressSemiconductor.pdf |
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The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations.
| Part Number | Description |
|---|---|
| CY7C1522AV18 | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1522KV18 | 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture |
| CY7C1522V18 | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1520KV18 | 72-Mbit DDR-II SRAM Two-Word Burst Architecture |
| CY7C1520V18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1521KV18 | 72-Mbit DDR II SRAM Four-Word Burst Architecture |
| CY7C1521V18 | 1.8V Synchronous Pipelined SRAM |
| CY7C1523AV18 | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1523JV18 | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1523KV18 | 72-Mbit DDR II SIO SRAM 2-Word Burst Architecture |
