CY7C1521KV18 Datasheet - Cypress Semiconductor

72-Mbit DDR II SRAM Four-Word Burst Architecture

* 72-Mbit Density (2M × 36)

* 250 MHz Clock for High Bandwidth

* Four-word Burst for reducing Address Bus Frequency

* Double Data Rate (DDR) Interfaces (data transferred at 500 MHz) at 250 MHz

* Two Input Clocks (K and K) for precise DDR Timing

* SRAM uses rising edges only

CY7C1521KV18

Cypress Semiconductor

596.77 KB

72-mbit ddr ii sram four-word burst architecture.

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