CY7C1520V18 Features
* 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
* 300 MHz clock for high bandwidth
* 2-word burst for reducing address bus frequency
* Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz
* Two input clocks (K and K) for precise DDR timing
* SRAM us
CY7C1516V18-CypressSemiconductor.pdf
Datasheet Details
CY7C1520V18, CY7C1516V18
Cypress Semiconductor
400.92 KB
1.8v synchronous pipelined sram.
This datasheet PDF includes multiple part numbers: CY7C1520V18, CY7C1516V18.
Please refer to the document for exact specifications by model.
📁 Related Datasheet
📌 All Tags
