* 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) * 300-MHz clock for high bandwidth * 4-Word burst for reducing address bus frequency * Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz * Two input clocks (K and K) for precise DDR
CY7C1517V18-CypressSemiconductor.pdf
Datasheet Details
CY7C1521V18, CY7C1517V18
Cypress Semiconductor
434.21 KB
1.8v synchronous pipelined sram.
This datasheet PDF includes multiple part numbers: CY7C1521V18, CY7C1517V18.
Please refer to the document for exact specifications by model.
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