ICS548A-03 divider equivalent, low skew clock inverter and divider.
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Packaged in 16-pin SOIC (150 mil) Input clock up to 160 MHz in the non-PLL mode Provides clock outputs of CLK, CLK, and CLK/2 Low skew.
that need to maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) modes should be used. This chip is n.
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