PCK2509SL driver equivalent, 50-150 mhz 1:9 sdram clock driver.
* Phase-Locked Loop Clock distribution for
PC100/PC133 SDRAM applications
* When outputs are disabled, the PLL and feedback output are
adjusted to 50 percent, .
* When outputs are disabled, the PLL and feedback output are
adjusted to 50 percent, independent of the duty cycle.
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