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PCK2509SL - 50-150 MHz 1:9 SDRAM clock driver

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General Description

The PCK2509SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Overview

INTEGRATED CIRCUITS PCK2509SL 50–150 MHz 1:9 SDRAM clock driver Product specification ICL03 — PC Motherboard ICs; Logic Products Group 2000 Dec 01 Philips Semiconductors Philips Semiconductors Product specification.

Key Features

  • Phase-Locked Loop Clock distribution for PC100/PC133 SDRAM.

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