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PLL205-04 - Programmable Clock Generator

Description

Name VDD1 VDD2 VDD3 VDD4 VDDL1 VDDL2 GND XIN XOUT PD# PCI_STOP CPU_STOP AGP_STOP REF_STOP PCI(0:8) Number 1 5 15,23 25 40 33 2,8,12,19,29, 32,37,43 3 4 34 35 36 44 45 10,11,13,14, 16,17,18,20,21 Type P P P P P P P I O I I I I I O Description Power supply for REF(0:1), REF_F and crystal oscillato

Features

  • PIN.

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Datasheet preview – PLL205-04

Datasheet Details

Part number PLL205-04
Manufacturer PhaseLink
File Size 260.11 KB
Description Programmable Clock Generator
Datasheet download datasheet PLL205-04 Datasheet
Additional preview pages of the PLL205-04 datasheet.

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Full PDF Text Transcription

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m Preliminary PLL205-04 o c . Programmable Clock Generator for VIA KT-266 Chipset U 4 t e FEATURES PIN CONFIGURATION e h • Generates all clock frequencies for VIA KT266 S chipset. a t • Support one pair of differential CPU clocks, one a pair of differential push-pull CPU clocks, 3 AGP .D and 10 PCI. w •w Enhanced PCI Output Drive selectable by I2C. w• One 48MHz clock and 24_48MHz clock via I2C. • • • • • • • • Three 3.3V AGP clocks. Three 14.318MHz reference clocks. Power management control to stop CPU, PCI, REF, 24_48MHz, 48MHz and AGP clocks. Supports 2-wire I2C serial bus interface with readback. Single byte micro-step linear Frequency Programming via I2C with glitch free smooth switching. Spread Spectrum ± 0.25% center, ± 0.5% center, ± 0.75% center, and 0 to -0.5% downspread.
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