PhaseLink PLL205-54
The internal clocks are disabled and the VCO and the crystal are stopped. When input is Low, it will stop PCI(0:8) and PCI9_E.| Part No. | PLL205-54 |
|---|---|
| Datasheet | PLL205-54 Download |
| Manufacturer |  PhaseLink |
| Description | Programmable Clock Generator |
| Buy | Stock & Price |
FEATURES
PIN CONFIGURATION e e● Generates all clock frequencies for VIA KT266 h chipset. S a
● Support one t pair of differential CPU clocks, one pair of a differential push-pull CPU clocks, 3 AGP and 10 PCI. D .
● w Enhanced PCI Output Drive selectable by I2C.
●w One 48MHz clock and 24_48MHz clock via I2C. w● Three 14.318MHz reference clocks. VDD1 GND 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF0/FS0*^ REF1/FS1*^ XIN XOUT REF_F REF_STOP#^ VDD2 48MHz/FS3*^ AGP_STOP#^ GND CPUT0 CPUC0
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● Program 5-bit CPU VID (Voltage Identification) through I2C. Power management control to stop CPU, PCI, REF, 24_48MHz, 48MHz and AGP clocks. Supports 2-wire I2C serial bus interface with readback. Single byte micro-step linear Frequency Programming via I2C with glitch free smooth switching. Built-in programmable watchdog timer. Spread Spectrum ± 0.25% center, ± 0.5% center, ± 0.75% center, and 0 to -0.5% downspread. 50% duty cycle with low jitter.
