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ICS8305 Datasheet

LVCMOS-to-LVCMOS/LVTTL Fanout Buffer

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Low Skew, 1-to-4 Multiplexed Differential/ ICS8305
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer
DATA SHEET
General Description
The ICS8305 is a low skew, 1-to-4, Differential/ LVCMOS-to-
LVCMOS/LVTTL Fanout Buffer. The ICS8305 has selectable clock
inputs that accept either differential or single ended input levels. The
clock enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the clock
enable pin. Outputs are forced LOW when the clock is disabled. A
separate output enable pin controls whether the outputs are in the
active or high impedance state.
Guaranteed output and part-to-part skew characteristics make the
ICS8305 ideal for those applications demanding well defined
performance and repeatability.
Features
Four LVCMOS / LVTTL outputs, 7output impedance
Selectable differential or LVCMOS / LVTTL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN Pullup
LVCMOS_CLK Pulldown
00
CLK Pulldown
nCLK Pullup/
11
Pulldown
CLK_SEL Pullup
D
Q
LE
OE Pullup
Pin Assignment
GND 1 16 Q0
OE 2
15 VDDO
VDD 3
CLK_EN 4
14 Q1
13 GND
Q0
CLK 5
12 Q2
nCLK 6
11 VDDO
CLK_SEL 7
10 Q3
Q1
LVCMOS_CLK 8
9 GND
Q2
ICS8305
Q3
16-Lead TSSOP
4.4mm x 3.0mm x 0.925mm package body
G Package
Top View
ICS8305AG REVISION C MAY 30, 2014
1
©2014 Integrated Device Technology, Inc.


Renesas Electronics Components Datasheet

ICS8305 Datasheet

LVCMOS-to-LVCMOS/LVTTL Fanout Buffer

No Preview Available !

ICS8305 Data Sheet
LOW SKEW, 1-TO-4 MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 9, 13
GND
Power
Power supply ground
2
OE
Input
Pullup
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS/LVTTL interface levels.
3
VDD
Power
Power supply pin.
4
CLK_EN
Input
Pullup
Synchronizing clock enable. When LOW, the output clocks are disabled.
When HIGH, output clocks are enabled. LVCMOS/LVTTL interface levels.
5
CLK
Input
Pulldown Non-inverting differential clock input.
6
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
7
CLK_SEL
Input
Pullup
Clock select input. When HIGH, selects CLK, nCLK inputs. When LOW,
selects LVCMOS_CLK input. LVCMOS/LVTTL interface levels.
8
LVCMOS_CLK
10, 12, 14, 16 Q3, Q2, Q1, Q0
Input
Output
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
Single-ended clock outputs. 7output impedance.
LVCMOS/LVTTL interface levels.
11, 15
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
RPULLUP
RPULLDOWN
CPD
ROUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
11
7
Maximum
Units
pF
k
k
pF
ICS8305AG REVISION C MAY 30, 2014
2
©2014 Integrated Device Technology, Inc.


Part Number ICS8305
Description LVCMOS-to-LVCMOS/LVTTL Fanout Buffer
Maker Renesas
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ICS8305 Datasheet PDF






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