uPD46184184B Description
The μPD46184184B is a 1,048,576-word by 18-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The μPD46184184B integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K and K#.
uPD46184184B Key Features
- 1.8 ± 0.1 V power supply
- 165-pin PLASTIC BGA (13 x 15)
- HSTL interface
- PLL circuitry for wide output data valid window and future frequency scaling
- Pipelined double data rate operation
- mon data input/output bus
- Two-tick burst for low DDR transaction size
- Two input clocks (K and K#) for precise DDR timing at clock rising edges only
- Two output clocks (C and C#) for precise flight time
- Internally self-timed write control