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K4S56323LF-FR - 2M x 32Bit x 4 Banks Mobile SDRAM

Download the K4S56323LF-FR datasheet PDF. This datasheet also covers the K4S56323LF-FE variant, as both devices belong to the same 2m x 32bit x 4 banks mobile sdram family and are provided as variant models within a single manufacturer datasheet.

Description

The K4S56323LF is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Features

  • VDD/VDDQ = 2.5V/2.5V.
  • LVCMOS compatible with multiplexed address.
  • Four banks operation.
  • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
  • EMRS cycle with address key programs.
  • All inputs are sampled at the positive going edge of the system clock.
  • Burst read single-bit write operation.
  • Special Function Support. -. PASR (Par.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (K4S56323LF-FE_Samsungsemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Samsung Semiconductor

Part Number Description
K4S56323LF-FC 2M x 32Bit x 4 Banks Mobile SDRAM
K4S56323LF-FE 2M x 32Bit x 4 Banks Mobile SDRAM
K4S56323LF-FHC 2M x 32Bit x 4 Banks Mobile SDRAM
K4S56323LF-FHE 2M x 32Bit x 4 Banks Mobile SDRAM
K4S56323LF-FHL 2M x 32Bit x 4 Banks Mobile SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
K4S56323LF - F(H)E/N/S/C/L/R 2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA FEATURES • VDD/VDDQ = 2.5V/2.5V • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) • DQM for masking. • Auto refresh. • • • • 64ms refresh period (4K cycle). Commercial Temperature Operation (-25°C ~ 70°C). Extended Temperature Operation (-25°C ~ 85°C).
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