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TC58NVG0S3AFT00 - 1 GBit CMOS NAND EPROM

General Description

The TC58NVG0S3A is a single 3.3-V 1G-bit (1,107,296,256 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048+64) bytes x 64 pages x 1024 blocks.

Key Features

  • x Organization Memory cell allay 2112 u 64K u 8 Register 2112 u 8 Page size 2112bytes Block size (128K  4K) bytes x Modes ReadResetAuto Page Program Auto Block EraseStatus Read x Mode control Serial inputoutput Command control x Powersupply VCC 2.7 V to 3.6 V x Program/Erase Cycles 1E5 Cycles(With ECC) x Access time Cell array to register 25 Psmax Serial Read Cycle 50 ns min x Operating current Read (50 ns cycle) 10 mA typ. Program (avg. ) 10 mA typ. Erase (avg. ) 10 mA typ. Standby 50 PA.

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Full PDF Text Transcription for TC58NVG0S3AFT00 (Reference)

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www.DataSheet4U.com TC58NVG0S3AFT00 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 1GBIT (128M u 8BITS) CMOS NAND E PROM DESCRIPTION The TC58NVG0S3A...

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OS 2 1GBIT (128M u 8BITS) CMOS NAND E PROM DESCRIPTION The TC58NVG0S3A is a single 3.3-V 1G-bit (1,107,296,256 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048+64) bytes x 64 pages x 1024 blocks. The device has a 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4Kbytes: 2112 bytes x 64 pages). The TC58NVG0S3A is a serial-type memory device which utilizes the I/O pins for both address and data input / o

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