ZL30105 Description
The ZL30105 SDH/PDH System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SDH and T1/E1 transmission equipment. It provides advanced support for systems deploying redundant clocks. The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network referenc.
ZL30105 Key Features
- Synchronizes to clock-and-sync-pair to maintain minimal phase skew between the master-clock and the redundant slave-cloc
- Supports ITU-T G.813 option 1, G.823 for 2048 kbit/s and G.824 for 1544 kbit/s interfaces
- Supports Telcordia GR-1244-CORE Stratum 3/4/4E
- Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
- Accepts three input references and synchronizes to any bination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384
- Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
- Holdover frequency accuracy of 1x10-8
- Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz
- Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, pliant with GR-253-CORE OC-3 and G.813 STM-1 specific
- Pb Free Matte Tin
ZL30105 Applications
- Synchronization and timing control for multi-trunk SDH and T1/E1 systems such as DSLAMs, Gateways and PBXs
- Clock and frame pulse source for AdvancedTCA™- and other time division multiplex (TDM) buses