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ZL30109 - DS1/E1 System Synchronizer

Datasheet Summary

Description

The ZL30109 DS1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk DS1 and E1 transmission equipment.

The 19.44 MHz output makes the ZL30109 also suitable for SDH line card applications.

Features

  • April 2010.
  • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E.
  • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces.
  • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces Ordering Information ZL30109QDG1 64 pin TQFP.
  • Trays, Bake & Drypack.
  • Pb Free Matte Tin -40°C to +85°C.
  • Simple hardware control interface.
  • Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.5.

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Datasheet Details

Part number ZL30109
Manufacturer Zarlink Semiconductor
File Size 452.49 KB
Description DS1/E1 System Synchronizer
Datasheet download datasheet ZL30109 Datasheet
Additional preview pages of the ZL30109 datasheet.

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Full PDF Text Transcription

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ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features April 2010 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces Ordering Information ZL30109QDG1 64 pin TQFP* Trays, Bake & Drypack *Pb Free Matte Tin -40°C to +85°C • Simple hardware control interface • Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs • Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz, 19.44 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.
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