A3S56D30GTP - 256M Double Data Rate Synchronous DRAM

Datasheet Summary

Description

A3S56D30GTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40GTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.

All control and address signals are referenced to the rising edge of CLK.

Features

- VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - CAS latency - 2 / 2.5 / 3 (programmable) Burst length - 2 / 4 / 8 (progr.

Zentel

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Datasheet Details

Part number	A3S56D30GTP
Manufacturer	Zentel
File Size	1.55 MB
Description	256M Double Data Rate Synchronous DRAM
Datasheet	A3S56D30GTP Datasheet
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A3S56D30GTP A3S56D40GTP 256M Double Data Rate Synchronous DRAM 256Mb DDR SDRAM Specification A3S56D30GTP A3S56D40GTP Zentel Electronics Corp. Revision 1.1 Jul., 2013 A3S56D30GTP A3S56D40GTP 256M Double Data Rate Synchronous DRAM General Description A3S56D30GTP is a 4-bank x 8,388,608-word x 8bit, A3S56D40GTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe ,and output data and data strobe are referenced on both edges of CLK. The A3S56D30/40GTP achieves very high speed clock rate up to 200 MHz . Features - VDD=VDDQ=2.5V+0.

Published: Sep 1, 2015 |