AS4C256M16D3LB-12BIN Datasheet - Alliance Semiconductor

AS4C256M16D3LB-12BIN, 4Gb DRAM

AS4C256M16D3LB-12BIN AS4C256M16D3LB-12BCN Revision History 4Gb AS4C256M16D3LB - 12BIN/BCN 96 ball FBGA PACKAGE Revision Rev 1.0 Rev 1.1 Details Pre.
Pin CK, CK CKE CS ODT RAS, CAS, WE DM (DMU), (DML) Type Input Input Input Input Input Input Function Clock : CK and CK are differential clock input.

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Datasheet Details

Part number:

AS4C256M16D3LB-12BIN

Manufacturer:

Alliance Semiconductor

File Size:

2.37 MB

Description:

4Gb DRAM

Features

* - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/received with data for capturing data at the receiver - DQS is edge-alig

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AS4C256M16D3LB-12BIN 4Gb DRAM Alliance Semiconductor

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