CY7C1312BV18

The CY7C1312BV18 is 1.8V Synchronous Pipelined SRAM designed by Cypress Semiconductor.

Product Overview

Cypress Semiconductor

Part number	CY7C1312BV18, CY7C1310BV18
Manufacturer	Cypress Semiconductor
File Size	390.16 KB
Description	1.8V Synchronous Pipelined SRAM
Datasheet	CY7C1310BV18-CypressSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: CY7C1312BV18, CY7C1310BV18. Please refer to the document for exact specifications by model.
Additional preview pages of the CY7C1312BV18 datasheet.

Separate independent read and write data ports.
Supports concurrent transactions.
250 MHz clock for high bandwidth.
2-word burst on all accesses.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 250 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simp.

📁 Similar Datasheet

CY7C131AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C131E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136AE - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C136E - 1K/2K x 8 Dual-Port Static RAM (Cypress)
CY7C1370C - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370CV25 - 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture (Cypress)
CY7C1370D - 18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM (Cypress)
CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture (Cypress)

Other Datasheets by Cypress Semiconductor

Published: Nov 6, 2016 |