CY7C1312KV18

The CY7C1312KV18 is 18-Mbit QDR II SRAM Two-Word Burst Architecture designed by Cypress Semiconductor.

Product Overview

Cypress Semiconductor

Part number	CY7C1312KV18
Manufacturer	Cypress Semiconductor
File Size	790.78 KB
Description	18-Mbit QDR II SRAM Two-Word Burst Architecture
Datasheet	CY7C1312KV18-CypressSemiconductor.pdf
Additional preview pages of the CY7C1312KV18 datasheet.

The CY7C1312KV18, and CY7C1314KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture.

Separate independent read and write data ports.
Supports concurrent transactions.
333 MHz clock for high bandwidth.
Two-word burst on all accesses.
Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) sim.

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Published: Mar 14, 2017 |