* Separate independent read and write data ports
* Supports concurrent transactions
* 333-MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
CY7C1313KV18 Datasheet (657.31 KB)
CY7C1313KV18
Cypress Semiconductor
657.31 KB
18-mbit qdr ii sram four-word burst architecture.
CY7C1311KV18/CY7C1911KV18 CY7C1313KV18/CY7C1315KV18
18-Mbit QDR® II SRAM Four-Word Burst Architecture
18-Mbit QDR® II SRAM Four-Word Burst Architec.
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