CY7C1317BV18

1.8V Synchronous Pipelined SRAM

Cypress Semiconductor

* Functional Description

* 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

* 300-MHz clock for high bandwidth

* 4-Word burst for reducing address bus frequency

* Double Data Rate (DDR) interfaces (data transferred at 600MHz) @ 300 MHz

* Two input clocks (

CY7C1317BV18

Cypress Semiconductor

447.88 KB

1.8v synchronous pipelined sram.

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