* Configurations CY7C1316KV18
* 2 M × 8 CY7C1916KV18
* 2 M × 9 CY7C1318KV18
* 1 M × 18 CY7C1320KV18
* 512 K × 36 18-Mbit density (2 M × 8, 2 M × 9, 1 M × 18, 512 K × 36) 333-MHz clock for high bandwidth Two-word burst for reducing address
CY7C1320KV18 Datasheet (1.45 MB)
CY7C1320KV18
Cypress Semiconductor
1.45 MB
18-mbit ddr ii sram two-word burst architecture.
CY7C1316KV18, CY7C1916KV18 CY7C1318KV18, CY7C1320KV18
18-Mbit DDR II SRAM Two-Word Burst Architecture
18-Mbit DDR II SRAM Two-Word Burst Architect.
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