Description
www.DataSheet4U.com CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture .
The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa.
Features
* Zero Bus Latency, no dead cycles between write and read cycles
* Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
* Fast clock speed: 133, 117, and 100 MHz
* Fast OE access time: 6.5, 7.0, and 7.5ns
* Internally synchronized registered outputs eliminate the nee
Applications
* Interleaved or linear four-word burst capability Individual byte write (BWa
