CY7C1357A - (CY7C1355A / CY7C1357A) 256K x 36/512K x 18 Synchronous Flow-Thru SRAM
The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa.
These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL).
They integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanc
CY7C1357A Features
* Zero Bus Latency, no dead cycles between write and read cycles
* Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
* Fast clock speed: 133, 117, and 100 MHz
* Fast OE access time: 6.5, 7.0, and 7.5ns
* Internally synchronized registered outputs eliminate the nee
