CY7C1357C - (CY7C1355C / CY7C1357C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
1] The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/ 512K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.
The CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency (NoBL) logic re
CY7C1357C Features
* No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
* Can support up to 133-MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin compatible and functionally equivalent to ZBT™ devices
* In
