CY7C1420KV18, CY7C1418KV18 Datasheet - Cypress Semiconductor

CY7C1420KV18 36-Mbit DDR II SRAM Two-Word Burst Architecture

The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K).

CY7C1420KV18 Features

* 36-Mbit density (2M × 18, 1M × 36)

* 333 MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz

* Two input clocks (K and K) for precise DDR timing

* SRAM uses rising edge

CY7C1418KV18-CypressSemiconductor.pdf

CY7C1420KV18 Datasheet Preview — This datasheet PDF includes multiple part numbers: CY7C1420KV18, CY7C1418KV18. Please refer to the document for exact specifications by model.

Datasheet Details

Part number:

CY7C1420KV18, CY7C1418KV18

Manufacturer:

Cypress Semiconductor

File Size:

777.80 KB

Description:

36-mbit ddr ii sram two-word burst architecture.

Note:

This datasheet PDF includes multiple part numbers: CY7C1420KV18, CY7C1418KV18.
Please refer to the document for exact specifications by model.

CY7C1420KV18 Distributor

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CY7C1420KV18 CY7C1418KV18 36-Mbit DDR SRAM Two-Word Burst Architecture Cypress Semiconductor