The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture.
The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for read and write are latched on alternate rising edges of the input (K)
CY7C1420KV18 Features
* 36-Mbit density (2M × 18, 1M × 36)
* 333 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
* Two input clocks (K and K) for precise DDR timing
* SRAM uses rising edge
CY7C1418KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1420KV18, CY7C1418KV18
Cypress Semiconductor
777.80 KB
36-mbit ddr ii sram two-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C1420KV18, CY7C1418KV18.
Please refer to the document for exact specifications by model.
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