CY7C1424KV18 - 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture
CY7C1424KV18 Features
* 36-Mbit density (2M × 18, 1M × 36)
* 333 MHz clock for high bandwidth
* Two-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
* Two input clocks (K and K) for precise DDR timing
* SRAM uses rising edge
