CY7C1424KV18, CY7C1423KV18 Datasheet - Cypress Semiconductor

CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture

CY7C1424KV18 Features

* 36-Mbit density (2M × 18, 1M × 36)

* 333 MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz

* Two input clocks (K and K) for precise DDR timing

* SRAM uses rising edge

Datasheet Details

CY7C1424KV18, CY7C1423KV18

Cypress Semiconductor

1.21 MB

36-mbit ddr ii sio sram two-word burst architecture.

This datasheet PDF includes multiple part numbers: CY7C1424KV18, CY7C1423KV18.
Please refer to the document for exact specifications by model.

CY7C1424KV18 Distributor

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