CY7C271
Cypress Semiconductor
237.78kb
32k x 8 power switched and reprogrammable prom. The CY7C271 and CY7C274 are high-performance 32,768-word by 8-bit CMOS PROMs. When disabled (CE HIGH), the 7C271/7C274 automatically
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CY7C274 - 32K x 8 Power Switched and Reprogrammable PROM
(Cypress Semiconductor)
1CY7C274
CY7C271 CY7C274
32K x 8 Power Switched and Reprogrammable PROM
Features
• CMOS for optimum speed/power • Windowed for reprogrammability • H.
CY7C277 - 32K x 8 Reprogrammable Registered PROM
(Cypress)
77
CY7C277
32K x 8 Reprogrammable Registered PROM
Features
• Windowed for reprogrammability • CMOS for optimum speed/power • High speed
— 30-ns addr.
CY7C2163KV18 - 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
(Cypress Semiconductor)
CY7C2163KV18/CY7C2165KV18
18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
18-Mbit QDR® II+ SRAM Four-Word Burst .
CY7C2165KV18 - 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
(Cypress Semiconductor)
CY7C2163KV18/CY7C2165KV18
18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
18-Mbit QDR® II+ SRAM Four-Word Burst .
CY7C2168KV18 - 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
(Cypress Semiconductor)
CY7C2168KV18/CY7C2170KV18
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
18-Mbit DDR II+ SRAM Two-Word Burst Arch.
CY7C2170KV18 - 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
(Cypress Semiconductor)
CY7C2168KV18/CY7C2170KV18
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
18-Mbit DDR II+ SRAM Two-Word Burst Arch.
CY7C2245KV18 - 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
(Cypress Semiconductor)
CY7C2245KV18
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture .
CY7C225 - 512 x 8 Registered PROM
(Cypress)
.
CY7C225A - 512 x 8 Registered PROM
(Cypress Semiconductor)
1CY7C225A
CY7C225A
512 x 8 Registered PROM
Features
• CMOS for optimum speed/power • High speed
— 25 ns address set-up
— 12 ns clock to output • Lo.
CY7C2262XV18 - 36-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture
(Cypress Semiconductor)
CY7C2262XV18/CY7C2264XV18
36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
36-Mbit QDR® II+ Xtreme SRAM Two.