Datasheet4U Logo Datasheet4U.com

M15F2G16128A-DEBG2L

16M x 16 Bit x 8 Banks DDR3 SDRAM

M15F2G16128A-DEBG2L Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchrono

M15F2G16128A-DEBG2L General Description

The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of.

M15F2G16128A-DEBG2L Datasheet (3.70 MB)

Preview of M15F2G16128A-DEBG2L PDF

Datasheet Details

Part number:

M15F2G16128A-DEBG2L

Manufacturer:

ESMT

File Size:

3.70 MB

Description:

16m x 16 bit x 8 banks ddr3 sdram.

📁 Related Datasheet

M15F2G16128A-DEBG2L - DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-DEBG2LS - DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-DEBG2LS - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-DEBIG2B - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DDR3 SDRAM Feature z Interface and Power Supply „ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) z JEDEC DDR3 Compliant „ 8n Prefetch Architecture „ Different.

M15F2G16128A-BDBG2F - 16M x 16 Bit x 8 Banks DDR III SDRAM (ESMT)
ESMT DDR III SDRAM Feature z 1.5V ± 0.075V (JEDEC Standard Power Supply) z Programmable CAS　Latency: 5, 6, 7, 8, 9, 10 and 11 z 8 Internal memory bank.

M15F2G16128A-BDBIG2B - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DDR3 SDRAM Feature z Interface and Power Supply „ SSTL_15: VDD/VDDQ = 1.5V(±0.075V) z JEDEC DDR3 Compliant „ 8n Prefetch Architecture „ Different.

M15F2G16128A-EFBG2L - DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-EFBG2L - 16M x 16 Bit x 8 Banks DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

M15F2G16128A-EFBG2LS - DDR3 SDRAM (ESMT)
ESMT DR3 SDRAM Feature  Interface and Power Supply ˗ SSTL_15: VDD/VDDQ = 1.5V(±0.075V)  JEDEC DDR3 Compliant ˗ 8n Prefetch Architecture ˗ Differenti.

TAGS

M15F2G16128A-DEBG2L 16M Bit Banks DDR3 SDRAM ESMT

Image Gallery

M15F2G16128A-DEBG2L Datasheet Preview Page 2 M15F2G16128A-DEBG2L Datasheet Preview Page 3

M15F2G16128A-DEBG2L Distributor