M15F2G16128A-EFBG2L Datasheet - ESMT

M15F2G16128A-EFBG2L, 16M x 16 Bit x 8 Banks DDR3 SDRAM

ESMT DR3 SDRAM .
The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation.

Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchrono

M15F2G16128A-EFBG2L-ESMT.pdf