AS4LC4M16S0 Datasheet (ETC) - 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

AS4LC4M16S0, 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

Output disable/write mask Address inputs Bank select inputs Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V ± 0.3V) Ground Clock input Clock enable AS4LC4M16S0 Selection guide Symbol Bus frequency Minimum clock access time Minimum setup time Minimum hold

AS4LC4M16S0 Features

* PC100/133 compliant

* Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16)

* Fully synchronous - All signals referenced to positive edge of clock

* Four internal banks controlled by BA0/BA1 (bank select)

* Hi